The ability to scale CMOS devices to smaller dimensions has allowed integrated circuits to experience continuous performance enhancements. Moreover, in spite of economic considerations, constraints on device designs and materials are hampering further improvements in scaling the devices. Since constraints in scaling are imposing fast approaching limits beyond which technical and economic constraints make additional scaling unappealing, new techniques have been developed to continuously increase the device performance.
One alternative which has gained popularity is to impose certain mechanical stresses within a semiconductor device substrate which can be advantageously used to modulate the device performance. For example, in silicon, hole mobility is enhanced when the silicon film is under compressive stress, while the electron mobility is enhanced when the silicon film is under tensile stress. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-FET and/or an n-FET in order to enhance the performance of such devices. However, the same stress component whether compressive or tensile, discriminatively affects the performance of the p-FET and the n-FET devices. Alternatively, compressive stress in the silicon, while it enhances the performance of the p-FET, it adversely affects the performance of the n-FET, while a tensile stress enhances the performance of the n-FET while adversely impacting the performance of the p-FET. Therefore, p-FET and n-FET require different types of stresses for performance enhancement, which imposes a challenge when concurrently fabricating high performance p-FET and n-FET devices, due to the difficulty in simultaneously applying compressive stress to the p-FET and tensile stress to the n-FET.
One approach for creating desired compressive and tensile stresses in the channel regions of p-FET and n-FET devices is to overlay the p-FET and the n-FET devices with separate compressive and tensile stressed dielectric films so that the tensile and compressive stresses can be respectively applied to the n-FET and p-FET devices.
Another problem of significance is the trend towards devices having smaller and smaller dimensions. Researchers have investigated the impact of technology scaling in reducing the effectiveness of virtually all known stress enhancement techniques. Channel stress from stressed liners is reduced with a tighter PC pitch, shorter polysilicon stacks and embedded SiGe (and embedded carbon), wherein the effectiveness is reduced with smaller RX-past-PC dimensions, for example. Hence, when migrating from one technology node to the next, one must find ways to overcome the degradation associated with scaling and find additional options to improve the technology performance further. Traditionally, this has been achieved by brute force, i.e., by way of higher stress liners, higher germanium content in eSiGe, and the like, or by significantly modifying the device materials/structure, such as embedded SiC.
Present day stress devices are currently manufactured with a stress inducing liner that is advantageously formed atop the gate region, the exposed surface of the substrate adjacent to the gate region and silicide contacts. An example of such stress devices is found, e.g., in U.S. Pat. No. 7,002,209 to Xiangdon Chen et al., of common assignee. The patent describes methods of forming a liner such that it contacts the sidewalls of the gate conductor. When thin sidewall spacers are used, the stress inducing liner is positioned on the thin sidewall spacer such that the thin sidewall spacer separates the stress inducing liner from the gate region. The stress inducing liner is deposited under conditions that create a compressive or a tensile stress. The method described in the aforementioned patent, however, is limited to the use of a single stress liner.
Another problem arising by the ever shrinking ground rules governing high performance technologies is caused by the loss of stress when reducing the pitch of the gate electrode conductor. This phenomenon has been described in the current literature, and more particularly in the paper “1-D and 2-D effects in uniaxially-strained dual etch stop layer stressor integrations” by Paul Grudowski et al., published in the Digest of Technical Papers of the 2006 Symposium on VLSI Technology. Therein are described a detailed electrical and simulation characterization of 2-D boundary effects and 1-D poly pitch response of highly stressed dual etch stop layer integrations, and how these effects impact achievable transistor performance gains and improved circuit designs. A contact etch stop layer used as a stressor has demonstrated significant performance improvements, particularly when employed in a dual integration. Still, the problem caused by continuously scaling down the devices remains.
A further problem imposed by traditional scaling methods is caused by the loss of stress when reducing the height of the gate electrode conductor. This phenomenon has also been described in the current literature, and more particularly in a paper “MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node” by S. Pidin et al., published in the Digest of Technical Papers of the 2004 Symposium on VLSI Technology. Therein is described a simulation characterization of device channel stress response to gate electrode height for highly stressed etch stop layers. Thus, a tradeoff is established between the traditional scaling benefits of gate height reduction, namely parasitic capacitance reduction due to a reduced gate sidewall area, and the stress imparted to the channel from a stressed liner.
In order to better appreciate the advantages, aspects and benefits of the present invention, prior art stressed complementary FET devices will now be described in order to distinguish the device structure of the present invention when it is compared to conventional prior art devices.
Referring to FIG. 1a, there is shown a pair of complementary FET devices (i.e., n-FET and p-FET) illustrating a first stress liner atop the transistor already patterned to induce the desired mobility gain. The first stress liner can be either tensile or compressive and thickness ranges from 40 nm-100 nm, with 50 nm being more typical. The stress liner in FIG. 1a is patterned using standard lithography and etching techniques where the stress liner is left on top of the devices that result in a mechanical strain favorable for increasing the mobility of the carriers. Tensile stress liners impart a stress that increases the electron mobility, while compressive stress liners impart a stress that increases the hole mobility. The stress liner is preferably any dielectric commonly used in semiconductor processing (SiN, SiO2, SiCOH, HfO2, SiCN, ZrO2), although SiN is preferably used.
Referring to FIG. 1b, the same pair of complementary FET devices are depicted having a second stress liner already patterned. The second stress liner should provide an opposing stress from that provided by the first stress liner and be removed from transistors that are covered by the first stress liner. For example, if the first stress liner is tensile, then the second stress liner should be compressive. The second stress liner should preferably have a thickness ranging from 40 nm-100 nm, with 50 nm being more typical. The second stress liner can be any of the standard dielectrics used in semiconductor processing (SiN, SiO2, SiCOH, HfO2, ZrO2, SiCN), although SiN is more commonly used.
Still referring to FIG. 1b, a thin oxide layer is deposited after patterning the first liner but before depositing the second liner in order to achieve etch selectivity if the second stress liner is made of a similar material as the first stress liner.
Next, referring to FIG. 2, another dielectric layer is deposited atop the silicon wafer. The dielectric is typically a low temperature SiO2 deposition with thickness ranging from 150 nm-250 nm, with 210 nm being more typical.
Referring to FIG. 3, the same semiconductor structure is illustrated after applying Chemical Mechanical Polish (CMP), resulting in the oxide being removed by this standard polishing step commonly used in semiconductor processing. The oxide is preferably removed until the top of the gate conductor electrodes are exposed, leaving no oxide. The final surface needs to be flat with no surface topography to have the surface directly above the target FET totally planarized.
The devices shown thus far suffer from a distinct degradation when the pitch between the complementary devices shrinks as the technology migrates from one node to the next. During the pitch reduction, the length of the stress nitride-silicon film interface is reduced, which in effect, reduces the stress coupling from the liner to the silicon film and MOSFET channel. In addition, the resulting stresses induced devices shown thus far remain susceptible to degradation from gate height reduction. This is because the stress in the channel is created by edge forces induced at the stressed-liner/sidewall spacer/silicon film intersection, the strength of which depend upon the poly height, as well as stressed-liner thickness, poly pitch, and the like.
Accordingly, there is a need in industry for a process of forming dual stress liners in which enhanced n-FET stress from a compressive cap can be achieved by reducing the polysilicon height without degradation during PC pitch scaling.